About

Venkata Srikanth Palanki is an experienced Computer Architecture and VLSI professional with over 8 years of relevant experience. Currently, he is working as a CPU Design Implementation Engineer at Apple, where he is responsible for designing and implementing CPU systems. Before his current role, Venkata worked as a CPU Design Implementation Intern at Apple, where he developed Synthesis flow automation in Perl and Shell to streamline tasks with minimal manual intervention. He also conducted experiments on CPU Floating Point unit from Synthesis through PnR to improve timing and area. Venkata proposed and made RTL changes in the Floating Point Unit Register file to save power, which was later taken through PnR for power number comparisons. He has extensive experience in RTL-to-GDS flow through micro-architecture understanding, synthesis, and place-and-route with aggressive targets for power, performance, and area. Venkata has also worked as a Physical Design Engineer I at LSI, where he worked on Physical Design of various complex sub-chip level blocks in 16nm FinFET technology from Floor planning to Sign-off. He worked on various STA issues and developed STA ECO fixes flow in PrimeTime DMSA. Venkata was one of the leads handling and advising 6+ team players, 20+ blocks in a sub-chip. He also aided in setting up the Multi-source CTS flow using IC Compiler and solved the issues seen with the timing correlation between pre-route vs. post-route vs. PrimeTime. Venkata holds a Master's degree in Electrical Engineering from the University of Minnesota, which he completed in 2016. He also holds a Bachelor's degree in Electronics and Communications Engineering from NIT Surathkal, which he completed in 2013. Venkata has a significant contribution to the 16nm design automation flow setup right from netlist quality check to PnR. He has developed various scripts in TCL to resolve timing and congestion issues, which helped in quick block closure.